SoC DESIGN

Best in class Spec to RTL Design and Verification

SoC DESIGN

SoCtronics has demonstrated proficiency in the design & implementation of multi-million gate chips on cutting edge process technologies upto 14nm. Our design experts help map product requirements and necessities, to our in house IP/SOC and design flows and/or tailor additional alternatives for further optimization of designs. Having executed numerous VLSI designs for both ASIC and FPGA, our dedicated team guarantees best in class time-to-market and first pass silicon success for complex SoCs.

OFFERING IN-HOUSE ADD-ONs

Expertise in various processor architectures

  • ARM, x86, MIPS, ARC and Tensilica

Proficiency in integrating and verifying various controller and bridge interface IP’s

  • PCIe, Ethernet, Display, SATA, HDMI, DDR, USB, MIPI MPHY, DPHY and Audio IPs
  • BVCI (ARC) to AHB/AXI bridge and PIF (Tensilica) to AHB/AXI bridge

Developed complex processor based SoC Verification environments using standard methodologies

  • Using/building Cadence VIP, System Verilog, Verilog, ‘C’ reference models, ‘E’ &Specman models
  • Automated Functional and Code coverage driven verification

Design for Test

  • Have vast experience in helping build test solutions and facilitating productization of high performance CPU & GPU class SOCs to cost sensitive mobile SOCs.
  • Solutions executed for various SOCs include Memory BIST including repair, Logic BIST, Boundary Scan Insertion (IEEE 1149.1 & 1149.6), Test Controllers, Scan insertion, Scan Compression, Automatic Test Pattern Generation and fault simulation.

FPGA Prototyping

The team gives customers a complete FPGA prototyping solution set. FPGA prototyping helps in first pass silicon success and speedier time to market.

Our specialists work with the FPGA vendors of the customer’s choice – Xilinx, Altera and so forth, to provide design partitioning, RTL design optimizations for FPGA, RTL design porting to FPGA, synthesizing and mapping the design onto FPGA. Likewise, we can also help in leveraging standalone PHYs or FPGA built-in SERDES for verifying the peripheral logic controllers along with helping customers port verification environment for FPGA verification and additionally perform netlist simulations according to necessity.

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