Strong Physical Design Pedigree

Full Chip Implementation

We have a strong expertise in taping out chips for various technologies and die sizes ranging from 180nm to 7nm and 3mm2 to 400mm2 respectively. The target market includes Compute, Graphics, Networking and Consumer. Also the team possess strong expertise in industry standard EDA tool suits from Cadence, Synopsys and Mentor Graphics. We have strong in house methodologies and automated flows which leads to quality closure and faster turnaround times.


Advanced Chip Builder Tool – ACT

Fully automated with user friendly interface.

Flat and hierarchical design configurability

configurability for design and resources (LSF , License etc.) and dynamic resource configuration

Smart Power – SMP

Advanced low power implementations

Best-in-class EDA flows with in house advancements

Leading high performance 40nm and 28nm designs

Rapid Characterization Engine – RaCE

Cell characterization and Library preparation

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