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SoC Synthesis/STA


Hands on experience with Logic Synthesis & Timing Analysis of multimillion gate SoC designs in cutting edge process technologies

  • Synthesis and STA activities on SoC designs with expertise in Constraints creation, CDC checks, Logical/Physical synthesis, Formal verification and Pre/Post Layout Timing closure

  • Expertise in Flat/Hierarchical SoC design synthesis while meeting PPA targets

  • Expertise in Timing constraints creation for FE/BE, time budgeting, constraints coverage analysis

  • Work closely with CAD teams and involve in synthesis/timing methodology development and improvement

Desired Skills and Experience:

  • B. Tech. / M. Tech. with 3-7 years of experience in Synthesis/STA

  • The candidate should be able to work on (Synthesis, DFT, FV, STA) and Timing closure on an SOC design

  • Should have handled Synthesis/STA for atleast 1-2 SoC designs on lower technology nodes

  • Knowledge of constraints writing for high speed designs with DDR, Serdes, USB interfaces is desirable

  • Experience on LP synthesis and Static power checks

  • Experienced in industry standard tools viz. Synopsys (DC/DC-T/DC-G, PT, GT, Formality), Cadence (RTLC, RCP, LEC)

  • Knowledge in TCL, Perl scripting is a must

Interested ? Apply now!

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