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Logic Design (RTL)

Hyderabad, Bengaluru

Motivated Digital Design Engineer with strong theoretical and practical background in high-speed design.

The candidate will be involved in designingEthernet, PCIe, SATA, and USB 3 supported SERDES protocol design.

Requirement of this job include:

  • Strong knowledgeable about the common high-speed serial data protocols

  • Experience with high speed digital circuits (e.g., serialize, deserializer, counters, dividers, etc.)

  • Experience in analyzing link budget for high-speed serial links

  • Good knowledge of different CDR/DFE Adaptation architectures

  • Good knowledge of TX/Rx equalization techniques

  • Experience in C/Matlab modeling of CDR loops a plus

  • Able to create block-level requirements from link budget analysis and models

  • Good experience in lab testing of high-speed serial links a plus

  • Knowledge of mixed signal concepts and data analysis tools

  • Working experience with Lint, CDC, Synthesis/P&R/STA, CTS, FPGA compiler tools


Define and Development of

  • Micro architecture, feasibility analysis, adaption and calibration algorithm,

  • RTL coding of high-speed digital/logic design, modeling of analog blocks;

  • Writing block-level test benches, debugging RTL and gate-level simulation failures;

  • Defining synthesis constraints, performing gate-level simulations;

  • Experience with SerDes based interfaces and protocols such as PCIe, SATA, SGMII,

  • XAUI, MIPI, is highly desirable.

  • Expertise in FPGA prototyping and FPGA validation is a plus.

  • Education background: MSEE plus at least 5+ years of digital design experience.

Interested ? Apply now!

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