World class work with friendly & talented team

AMS Verification



  • You will be part of a highly skilled high speed PHY design team working on challenging high speed PHY in latest foundry nodes (28nm, 14nm and below). Most of the work will be in DDR3/4 and LPDDR3/4 designs.

  • You will undertake mixed-signal verification of high speed analog/mixed signal designs of significant complexity and ensure digital analog boundary correctness.

  • You will need to become familiar with micro-architecture and protocol and identify areas of verification that cannot be easily covered by conventional digital verification process. You will need to come up with verification plans and drive implementation of those plans across digital and analog boundaries

  • You will drive behavioral modelling effort of analog blocks in various forms. Verilog-A, system Verilog, real modelling and IBIS models. You will also develop test benches to check circuit against model.

  • You will help generate analog macro netlists and run and debug digital regression smoke-screen tests to ensure initial quality of analog macros.


  • 4-12 yrs. experience in mixed-signal verification and behavioral modelling of analog blocks

  • Bachelor’s or Master’s degree in Electrical Engineering

Required Qualifications:

  • Exposure to verification of complex high speed PHY and/or complex analog blocks.

  • Exposure to modelling and validating complex analog circuits in Verilog-D, Verilog-A

  • Familiarity with industry standard system Verilog, AMS tools and environments including understanding tradeoffs between accuracy and turnaround time

  • For senior candidates (8+ yrs.):

  • proven track record of having verified complex mixed signal designs using state of the art flows and tools

  • proven track record of being able to identify and execute on AMS test plans including creating re-usable test benches

  • refine AMS and modelling flows and methods to achieve better efficiency and quality

Desired qualifications:

  • Protocol level understanding of DDR and prior work in AMS verification of DDR or other high speed PHY architecture is big plus.

  • Experience with industry standard tools such as Cadence ADE, Spectre, IRUN, UVM etc.

  • Familiarity with matlab, wreal and its use for modelling complex analog blocks

  • Ability to work & communicate with cross functional teams, overseas teams, and strong oral & written communication skills

  • Problem solver with good attitude and commitment

  • Ability to mentor and mold junior engineers (for senior candidates, 8+ yrs.)

Interested ? Apply now!

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