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Are you looking for a career in
VLSI design engineering?
SoCtronics has great opportunities for you. We look for someone who enjoys overcoming challenges, and who get satisfaction from doing what others thought couldn’t be done.If you’re ready to explore the limits of your potential and do great things, you belong on our team.

SoC Design

Experienced Design Engineer to lead design efforts of complex processor based SOCs. The candidate must have demonstrated success in atleast one project involving design of complex digital FPGAs/ASICs. Will be expected to lead design on one or more SOCs/Subsystems and be responsible for understanding System functionality, translate design requirements properly to meet the SOC performance, power and cost goals and to attain high design quality by utilizing latest methodologies. Expected to support pre and post silicon design validation as required.

Experience : 6-15 years

The successful candidate should demonstrate:

  • Excellent critical thinking & problem solving
  • Excellent communication and technical writing capability
  • Systems level thinking/awareness of big-picture
  • Ability to understand and own complex problems
  • Ability to work in a fast paced and dynamic environment
  • Ability to capture requirements interacting with customers and translate them to design specification
  • Ability to structure design efforts/work break down and track deliverables as per plan

Responsibilities:

  • Lead SOC Design of Complex SOCs (2-10Million gate SOCs) for delivery to customer
  • Micro architecture and specification documentation
  • Logic design and Verilog RTL development
  • Shared responsibility for design-for-test and timing-closure
  • Support for Verification, Emulation and Validation activities
  • Work with Architecture team to ensure the performance and power goals are met
  • Lead the design of SOC Clocking, Reset, Fuses, Security etc as per the application requirements

Experience, Skills & Education Required:

  • BSEE or MSEE with 6-9 plus years of experience in chip design including successful completion of high speed and complex IC’s
  • Good knowledge of SOC design process, digital design, CDC, LINT tools and techniques
  • Experience with 3rd party IP evaluation, selection & integration
  • Experience debugging in the LAB and Silicon/FPGA issues on the bench
  • Working knowledge in Electrical analysis and debug is a plus
  • Working knowledge and trade-off analysis in performance modeling is desirable
  • Excellent Verilog RTL coding style with eye on performance and optimization of logic
  • Scripting and automation skills: Unix/Linux shell programming, Perl, Tcl/Tk, Python, etc
  • Hand on working experience with industry standard tools and methodologies for CDC, LINT and Timing Closure
  • Experience with integration of embedded processors like ARM, MIPS etc is a plus
  • Hand on Experience in implementation of Low power management features like Isolation cells, Level Shifters, Retention cells is a must
  • Must have working knowledge in any one or two protocols like PCIe, SATA, DDR, Ethernet, SD/SDIO/eMMC, MIPI, AMBA etc.,
  • Should have worked on productisation of atleast one SOC as per the customer requirement
  • Good working knowledge on FPGA/Emulator is desirable

SoC Verification

Experienced Verification Engineer to lead verification efforts of complex processor based SOCs. The candidate must have demonstrated success in atleast one project involving verification of complex digital FPGAs/ASICs. Will be expected to lead verification on one or more SOCs/Subsystems and be responsible for understanding design functionality, developing test plans, designing/developing verification environment, and generating the necessary tests to attain high design quality. Expected to support pre and post silicon design validation as required.

Experience : 6-15 years

The successful candidate should demonstrate:

  • Excellent critical thinking & problem solving
  • Strong verification and advanced debugging skills
  • Systems level thinking/awareness of big-picture
  • Ability to understand and own complex problems
  • Ability to translate design specifications into test requirements
  • Ability to identify corner cases, performance issues and target them in verification
  • Ability to structure verification efforts/work break down and track deliverables as per plan

Responsibilities:

  • Lead SOC Verification of Complex SOCs for delivery to customer
  • Develop SOC Verification Requirement Documentation and Coverage based verification goals
  • Work closely with Design teams to properly track, close and follow up on Bugs
  • Work with Architecture team to close on performance goals
  • Shared responsibility for pre-silicon Validation on FPGA/Emulator. Close interaction with Software team
  • Support for IP verification and SOC integration of IP testbench

Experience, Skills & Education Required:

  • BSEE or MSEE with 6-9 plus years of experience in digital SOC design verification
  • Good knowledge of SOC design verification process, verification tools and techniques
  • Design verification experience (developing test plan, test bench, tests, assertions, functional & code coverage, debugging tests and designs)
  • Familiarity with design, verification and assertion languages
  • Working knowledge of Verilog and SystemVerilog is required; SystemC is a plus
  • Working knowledge of C programming; C++/OO coding principles a plus
  • Scripting and automation skills: Unix/Linux shell programming, Perl, Tcl/Tk, Python, etc.
  • Hand on working experience with industry standard tools and methodologies like OVM or UVM
  • Experience with embedded processors like ARM, MIPS and firmware development a plus
  • Experience in verification of power management features and Low power features is a plus
  • Prior working knowledge in any one or two protocols like PCIe, SATA, DDR, Ethernet, SD/SDIO/eMMC, MIPI, AMBA etc.,
  • Experience in verification CAD is a plus
  • Working knowledge on Cadence or Mentor VIPs

Physical Design

  • Expertise in implementation TOP LEVEL / COMPLEX BLOCK LEVEL of multimillion gate SoC designs
  • Technology: 28nm / 32nm/ 45nm / 65nm Technologies
  • Design Complexity: Greater than 1Mn and up to 40Mn Gates
  • Tools / Flows: Expertise in Magma (Talus) / Synopsys (ICC) / Cadence (SoC Encounter). Tools is a must, Scripting using TCL / Perl Desirable

Skills

Should have very good conceptual understanding of the technology, design flow and implementation. Should have worked on all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out. Should be able to interface with Front End Design team to resolve Design Issues.

  • Experience level : 6+ years
  • Location: Bay Area
  • Education : BE, BS, MS, ME * Electronics, Computer Science

Analog Design

    • Experience: 6 – 12 years

Desirable Experience:

Design & develop analog/mixed signal CMOS circuits in deep sub-micron technologies (65nm – 10nm) in one or more of the following:

      • A/D, D/A converters
      • PLL & DLL circuits
      • High speed Serdes Interfaces (1Gbps-30Gbps)
      • High speed Memory interfaces (DDR3/4, LPDDR3/4, HMC, HBM)
      • I/O cell designs: LVTTL/LVCMOS, LVDS, HSTL, SSTL, ESD protection cellse
      • Analog building blocks: Voltage regulators, Bandgap generators, Temp sensors, high speed amplifiers & comparators.

  • Create Verilog/verilog-A behavioral models
  • Perform cell characterization & create cell level timing (.LIB) models.
  • Create test benches, simulate, run, verify, & analyze spice & mixed modes sims
  • Supervise &guide layout work
  • Perform post-layout verification, EM/IR analysis, reliability checks
  • Create block level & macro level specs and verify
  • Participate in silicon bring up, characterization, & perform Si correlations against models & simulations

Requirements:

  • Minimum requirement: Master’s degree with 3+ years of relevant experience
  • Experience with industry standard tools such as Spectre, Hspice, AMS verification, EM/IR flows & tools (Apache, Voltus), MATLAB, Calibre/StarRC, Apache, Voltus
  • Working experience with one more of the PHY designs for the following protocols: MIPI M-PHY, D-PHY, PCIe1/2/3, SATA1/2/3, 10GKR, XFI, HMC, HBM, DDR3/4, & LPDDR3/4
  • Experience with transistor level & block level designs
  • Thorough understanding of design rules, & knowledge of physical design verification (LVS/DRC/ERC/Extraction)
  • Understanding of Mismatch analysis & MonteCarlo methodology/sims, transistor level & Circuit level noise analysis
  • Understanding of device physics & deep-sub micron issues
  • Knowledge of Unix/Linux env, and scripting (Tcl, SKILL, or Perl)
  • Ability to work & communicate with cross functional teams, overseas teams, and strong oral & written communication skills.

CAD Engineers

    • Experience: 6 – 12 years

Desirable Experience:

Expertise on one or more of the following:

      • Define/develop analog/mixed signal custom design flow
      • Tool expertise, automation, & customization in Schematic capture, custom layouts, custom placement, & custom routes in cadence analog design environment
      • Design and develop full custom reference flows with standard EDA tools
      • Design and develop automation flows as required for design engineers & layout engineers
      • Design and develop flows for reliability checks including EM/IR, device reliability checks
      • Interface with design team at multiple locations, understand & resolve problems
      • PDK installation, support, & maintenance
      • Design & develop QA flows
      • Automation of Library development, Characterization, view generation, & QA checks for standard cells, I/O cell libraries,
      • Automation of IP level datasheet generation, & customer releases
      • Interface with EDA vendors, internal IT teams, internal development teams in enhancing company’s productivity & optimizing EDA licensing utilization

Requirements:

  • Minimum requirement: Bachelor’s degree in EE or CS with 5+ years of relevant experience
  • Expertise in SKILL, & Ocean scripts, Cadence ADE environment, Virtuoso, Spectre & AMS simulators
  • Proficiency in setting up flows for LVS/DRC/ERC/XRC flows using Mentor Calibre and StarRC
  • Knowledge of CVS & SOS revision control systems
  • Expertise in one more of the scripting languages: SKILL, Tcl, Perl, Shell, Python, C/C++
  • Understanding of Devise physics & CMOS circuits
  • Understanding of device physics & deep-sub micron issues
  • Knowledge of Unix/Linux env, and scripting (Tcl, SKILL, or Perl)
  • Good understanding of entire IC design/development flow
  • Ability to work & communicate with cross functional teams, overseas teams, and strong oral & written communication skills
  • Understanding of Memory compiler software is a plus

Embedded Software

  • System Engineering
  • Senior / Lead Level Engineers
  • Experience : 6+ years
  • Must have:
    • Experience in PCB design, FPGA Validation and Debugging.
    • Familiarity with all lab instruments like high-frequency oscilloscopes, Logic Analyzers, Pattern Generators, Signal Analyzers.
    • Familiarity with FPGA porting methods, script file development, timing closure, FPGA Netlist Simulations, FPGA debug using chip-scope or similar tool.
    • JTAG based debug on board, driver development, ability to write C code, ability to debug on the board to resolve problems.

Desirable:

  • Familiarity with high-speed board design and debug methods. Knowledge about Signal Integrity and Characterization.
  • Software Engineering
  • Senior / Lead Level Engineers
  • Experience : 6+ Years
  • Must have:
    • BSCS/BSEE degree.
    • Background in embedded systems
    • Software/firmware development for embedded processors
    • Development on embedded Linux
    • Debug of complex real time systems
    • Multimedia FW for audio, video and graphics products
    • Must be comfortable with the hardware/software interface, low level control of hardware, silicon and FPGA systems, systems and silicon bring-up and debug
    • Experience in proven delivery of complex projects, bug free coding, revision control systems, continuous code improvement, tracking tools and process

Desirable:

MSCS/MSEE degree, Experience using network protocol stacks (TCP/IP, UDP, RTP) for multimedia applications, experience with UPnP and DLNA at the protocol level, Network security protocols (IPSec, DTCP-IP), graphics libraries and rendering (Direct FB, OpenGLES), development. Experience on RTOS (VxWorks, Integrity, ThreadX, Free RTOS etc.), Knowledge of the HDMI/DVI, I2C, Ethernet and Wi-Fi protocols.

Applicants should have good leadership qualities and excellent communication skills.

To apply for any of the above positions send your resume to careers@soctronics.com