Low Power Lead
Job Title: Low Power Lead
Job Qualification: B. Tech. / M. Tech.
Job Experience: 5-8 years of experience in LP implementation and verification
Job Location: Hyderabad, Bengaluru
Hands on experience in leading Low Power Feature implementation and verification on SoC designs with more than 3 power/voltage domains. In depth knowledge of low power design methodologies and Checks.
- Understand the design and implement multiple low power features by creating/modifying low power intent for the design using UPF/CPF
- Verify the implementation of a variety of lowpower features, and deliver a fully verified, synthesis/timing clean design for PnR
- Responsible for supporting PnR team in implementation and verification of low power infrastructure in backend design
- Responsible for debugging low power design issues along with current tool and flow issues
- Work closely with CAD teams and involve in methodology development and improvement
- Own SoC Low power feature implementation and verification activities while managing a team of 4-5 engineers
Desired Skills and Experience:
- The candidate should be able to work with and lead a team of engineers working on LP feature implementation (Power gating, Multi-Voltage, Retention, etc.) and verification on SOC designs
- Should have handled LP feature implementation and verification work for atleast 2-3 SoC designs with more than 3 power domains on lower technology nodes
- Command on UPF based synthesis, low power LEC and CLP checks at RTL/gate level.
- Good understanding of switch matrix design and simulations
- Working (hands on) knowledge on static LP checks and switch matrix analysis using PTPX, Redhawk, LEC, CLP, VC LP, Spyglass, MVRC
- Knowledge in TCL, Perl scripting is a plus
To apply please send resumes to Email: firstname.lastname@example.org