SoC Synthesis/STA Lead

Job Title: SoC Synthesis/STA Lead

Job Qualification: B. Tech. / M. Tech.

Job Experience: 5-10 years of experience in Synthesis/STA

Job Location: Hyderabad, Bengaluru

Hands on experience with Logic Synthesis & Timing Analysis of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)

  • Lead Synthesis and STA activities on SoC designs with expertise in Constraints creation, CDC checks, Logical/Physical synthesis, Formal verification and Pre/Post Layout Timing closure
  • Expertise in Flat/Hierarchical SoC design synthesis while meeting PPA targets
  • Expertise in Timing constraints creation for FE/BE, time budgeting, constraints coverage analysis, Timing closure techniques in MMMC environment
  • Work closely with CAD teams and involve in synthesis/timing methodology development and improvement
  • Own SoC synthesis/timing activities while managing a team of 5-10 engineers

Desired Skills and Experience:

  • The candidate should be able to work with and lead a team of engineers working on FE design(Synthesis, DFT, FV, STA) and Timing closure on an SOC design
  • Should have handled Synthesis/STA for atleast 2-3 SoC designs on lower technology nodes
  • Excellent understanding of timing closure techniques & SI analysis/fixes in lower technology nodes in high speed designs with DDR, Serdes, USB interfaces
  • Experience on LP synthesis and Static power checks
  • Experienced in industry standard tools viz. Synopsys (DC/DC-T/DC-G, PT, GT, Formality), Cadence (RTLC, RCP, LEC, Tempus)
  • Knowledge in TCL, Perl scripting is a must

To apply please send resumes to Email: